The semiconductor industry roadmap calls for lowering the dielectric constant on the insulation surrounding multi-level on-chip interconnects. The dielectric constant must be lowered so as to reduce the parasitic capacitive load to the integrated circuits, as well as to reduce the capacitive coupling between neighboring interconnects.
Reducing dielectric constant often comes with a concomitant reduction in insulator mechanical properties such as modulus, hardness, thermal conductivity and fracture toughness. Significant stresses can develop in the structure due to thermal expansion mismatches with the substrate and the metal interconnects. These stresses can cause fatigue of copper vias or studs during thermal cycling, resulting in yield or reliability problems. A method is therefore needed to improve the strength of vias that are fabricated in low-k materials.
The strength of vias may be improved using a refractory metal instead of copper for the via, or by increasing the thickness of the refractory metal liner surrounding the via as compared to the line conductor. Heretofore, formation of interconnect structures having different materials or different liner thicknesses for the vias and lines could be achieved only by using a series of single damascene fabrication steps. Specifically, a via-level dielectric layer is first deposited, then a via opening is formed in the dielectric material, and then the via is filled with a first conductive material. Excess conductive material is removed by, e.g., chemical mechanical polishing (CMP) to make the top surface of the via coplanar with the top surface of the via-level dielectric. The line-level dielectric is next deposited, a trench opening is formed in the line-level dielectric overlying the via, and the trench is filled with a second conductive material. Again, excess conductive material must be removed by, e.g., CMP to make the top surface of the line conductor coplanar with the top surface of the line-level dielectric.
This series of single damascene steps is time-consuming and expensive. Moreover, two separate layers of dielectric (via-level and line-level) exhibit inferior electrical characteristics as compared to a single layer of dielectric material such as that found in a typical dual damascene structure.
Thus, there is a need in the art for a method of forming a dual damascene interconnect structure having a single layer of dielectric material for the via and line levels, but different materials or different liner thicknesses for the vias and lines.